As integrated circuits increase in size and complexity, test compression is becoming a requirement for reducing test data volume and test application time. Test compression compresses the amount of both stimuli and response data that must be stored in an automatic test equipment (ATE).
Test stimulus compression is done by adding a decompressor at the scan input side of the scan chains for decompressing n-input compressed test patterns stored in the ATE to m-input decompressed test patterns for driving m internal scan chains during each scan shift cycle, where n<m. The decompressor can be a linear feedback shift register (LFSR) based finite-state machine or a combinational logic network using a multiplexer (MUX) network or exclusive-OR (XOR) network. When a combinational logic network is used, the decompressor is also referred to as a broadcaster.
Test response compaction is done by adding a compactor at the scan output side of the scan chains for compacting the m-output decompressed test response of the scan chains to an n-output compressed test response during each scan shift cycle, where n<m. The compactor can be a time compactor, a finite-memory compactor or a Space compactor. Both time compactor and finite-memory compactor are sequential circuits. Space compactors are often built out of XOR or Exclusive-NOR (XNOR) networks and do not contain storage elements. FIG. 1 shows a Space compactor using an XOR tree. Space compactor cone N is defined as the logics back-traceable, until a compactor input is reached, from compactor output index N. Scan chains to be compacted and observed via a specific Space compactor output N are referred to as driver chains for the Space compactor cone N. For example, in FIG. 1, the scan chains 110, 111, 112 and 113 are driver chains for the first Space compactor cone (distinguished by the first output SO1 120), scan chains 114, 115, 116, 117, 118 and 119 are driver chains for the second Space compactor cone (distinguished by the second output SO2 121). If values captured by scan cells are shifting into the same Space compactor cone at the same cycle, the scan cells are said to be “compacting in step”. For example, if scan chain 114 has M scan cells, scan chain 115 has L scan cells and we use SC(A, B) to represent B-th scan cell of chain A, then SC(114, M) and SC(15, L), SC(114, M−1) and SC(115, L−1), SC(114, M−2) and SC(115, L−2), etc. are compacting in step.
In scan-based designs, a certain number of scan cells may capture unknown (X) values during capture cycle. Potential sources of X's can come from an uninitialized memory, black box, bus contention, non-scan latches and flip-flops, floating bus, multi-cycle paths, cross-clock-domain logic, etc. These X's are generally repaired at the design stage in order to increase the circuit's fault coverage. However, some X's, like races, may become known very late at the design or manufacturing stage, and thus cannot be repaired. Once captured by scan cells, these X values will be injected to the compactor during response compaction. Since a time compactor is LFSR-based with output feeding back to its inputs, once an X value is injected, the X will stay in the compactor and thus destroy its signature. Because a finite-memory compactor is usually shift-register-based, the X will stay only for a few clock cycles in the compactor before being flushed out. In the Space compactor's case, since it contains no storage elements and feedback paths, the X can be shifted out in one single clock cycle.
When using a Space compactor, if a scan cell with a captured fault effect is compacting in step with a scan cell with a captured X value, the fault effect might be masked by the X value during compaction and cannot be detected by the ATE. This problem is called X-induced masking. A scan cell capturing X value and is expected to cause a specific X-induced masking effect in the single-fault model is called the X-masking scan cell and scan cells capturing fault effects yet masked by the X-masking scan cell are called the victim scan cells. Note that a victim cell is always compacting in step with a X-masking scan cell in a Space compactor. A scan chain containing X-masking scan cell(s) is called the X-masking scan chain. If two or more scan cells with captured fault effects are compacting in step but eventually the fault effects cancel each other out during compaction, the problem is called Error masking (Aliasing). Scan cells causing a specific Aliasing effect in the single-fault model are called the Aliasing scan cells and scan chains containing Aliasing scan cells are called the Aliasing scan chains. Aliasing scan cells are always compacting in step in a Space compactor. The circuit's fault coverage might decrease due to X-induced masking and Error masking when a compactor is used.
Since X values may mask fault effects, various compactors have been developed in the literature to reduce X impact. For example, the X-compact, which is one type of X tolerant compactor, proposed by Mitra et al. (2004) generally comprises internal scan chain outputs connected to more than one XOR gate in an XOR tree. This compactor, however, cannot tolerate circuits with many X values appearing at the scan channels. The selective compactor described in the U.S. patent application Ser. No. 10/973,522 by Rajski et al. (2004) can selectively mask X's on scan chains to avoid X-induced masking by using selective registers. However, this compactor needs additional registers (storage elements) and decoding logic to block X-value propagation.
A scalable compactor described by Wohl et al. (2004) is shown in FIG. 2. This prior art solution uses pure multiplexer (MUX) networks as scan output selectors with full X-tolerant and scan-based diagnosis ability. It relies on selective observation of scan chain outputs without using an XOR tree to compact the response data. However, it needs many additional input pins to select scan chain outputs. It also reduces the ATPG dynamical compaction ability because only a small fraction of scan outputs can be used for observation.
Convolutional compactor and block compactor were described in the U.S. patent application Ser. No. 10/778,950 by Rajski, et al. (2004) and the paper by Wang, et al. (2003), respectively. These prior art solutions proposed finite memory compactors to generate a signature of response data in several scan cycles. FIG. 3 is a finite memory compactor comprising an injector network (using XOR gates), storage elements, and an optional switch network. The compactor has limited X tolerant ability since X-values that are fed into the compactor can be clocked out after a finite clock cycles.
Therefore, there is a need to improve upon the current Space compactor with high compaction capability and without heavy area overhead to solve the X-induced masking and error masking problems. In addition, this solution should further allow provision to perform scan debug, diagnosis and yield improvement of the DFT methodologies utilizing embedded scan chains possibly without impacting the speed at which the scan operation is performed.